Senior RTL Verification Engineer – SV/UVM Lead

Mogi I/O : OTT/Podcast/Short Video Apps for you; Belton (TX); On-site; USD 160,000 - 180,000; Full time

Job summary

A leading tech company in Texas is seeking a Verification Engineer to lead RTL design verification for high-speed digital systems. This role involves developing verification plans, building SV/UVM environments, and ensuring full functional coverage while collaborating with cross-functional teams. Candidates should have over 5 years of experience in digital engineering with at least 3 years in design verification, and possess strong debugging skills. Competitive compensation of $160,000 - $180,000 is offered.

Qualifications

• Over 5 years of experience in digital/RTL engineering required.
• At least 3 years in design verification is mandatory.
• Strong knowledge of VLSI verification flows essential.

Responsibilities

• Lead RTL design verification for high-speed digital systems.
• Develop and execute verification plans based on design specs.
• Build and maintain SV/UVM environments.

Skills

Digital/RTL engineering

Design verification

VLSI verification flows

SystemVerilog & UVM

Debugging skills

Job description

A leading tech company in Texas is seeking a Verification Engineer to lead RTL design verification for high-speed digital systems. This role involves developing verification plans, building SV/UVM environments, and ensuring full functional coverage while collaborating with cross-functional teams. Candidates should have over 5 years of experience in digital engineering with at least 3 years in design verification, and possess strong debugging skills. Competitive compensation of $160,000 - $180,000 is offered.