Senior Verification Engineer - Mixed-Signal ICs

Cirrus Logic; Chandler (AZ); On-site; USD 90,000 - 130,000; Full time

Job summary

A leader in silicon design is looking for an experienced Design Verification Engineer in Chandler, Arizona. You will collaborate with cross-functional teams to ensure high-quality mixed-signal IC solutions through end-to-end functional verification. Candidates should have a background in electrical engineering, relevant experience in ASIC verification, and strong proficiency in Verilog and SystemVerilog. This role provides opportunities to work on advanced verification methodologies in a collaborative environment.

Qualifications

• Bachelor’s with 2+ years of relevant experience.
• Master’s with 0+ years of relevant experience.
• Ability to work effectively in a cross‑disciplinary, team‑oriented environment.

Responsibilities

• Develop comprehensive verification plans aligned with design and system requirements.
• Perform functional verification of custom mixed-signal ASICs at block and chip level.
• Design and implement UVM-based testbenches, including infrastructure and assertions.

Skills

Proficiency with HDLs: Verilog and/or VHDL

Proficiency with HVLs: SystemVerilog with UVM

Understanding of digital design principles

Testbench architecture and stimulus generation

Regression execution and debug

Coverage analysis and closure

Effective collaboration in a team environment

Education

Bachelor’s, Master’s, or PhD in Electrical Engineering

Job description

A leader in silicon design is looking for an experienced Design Verification Engineer in Chandler, Arizona. You will collaborate with cross-functional teams to ensure high-quality mixed-signal IC solutions through end-to-end functional verification. Candidates should have a background in electrical engineering, relevant experience in ASIC verification, and strong proficiency in Verilog and SystemVerilog. This role provides opportunities to work on advanced verification methodologies in a collaborative environment.