Senior Verification Engineer - SoC/FPGA & AI-Driven

Microchip Technology Inc.; Roseville (CA); Sur place; USD 91 000 - 232 000; Plein temps

Avantages offerts par ce poste

Health benefits from day one

Restricted stock units

ESPP program

Résumé du poste

Microchip Technology Inc. in Chandler, Arizona, seeks an experienced verification engineer to join the FPGA Business Unit and help verify next‑generation, secure, low‑power FPGA devices.

You will design and maintain UVM test benches, perform RTL and post‑silicon verification, collaborate with architecture, design, and emulation teams, and mentor junior engineers while advancing AI/ML‑based verification methodologies.

Qualifications

• 12.5+ years in functional verification of complex SoC designs.
• Expertise in SystemVerilog, UVM, formal verification methodologies.
• Familiarity with AI/ML-driven EDA tools and scripting for flow integration.

Responsabilités

• Verification of complex subsystems and SoC using an optimal combination of constrained random, formal and C based verification methodologies.
• Develop and maintain highly reusable UVM based test benches and verification environments.
• Involve in RTL, power aware and gate level verification.
• Contribute to quality and productivity by using AI/ML-enabled verification methodologies
• Collaborate with emulation and hardware prototyping teams to define a unified verification methodology.
• Collaborate with architecture and design teams to ensure seamless execution and first-silicon success.
• Mentor junior team members.

Connaissances

SystemVerilog

UVM

Formal verification

C/C++

Python

RTL verification

AI/ML tooling

Emulation

Git/Perforce

Security IPs

Formation

BS or MS in Electrical/Electronic Engineering

Outils

Cadence verification suites

Synopsys verification suites

Siemens verification suites

Git

Perforce

SVN

Description du poste

Microchip Technology Inc. in Chandler, Arizona, seeks an experienced verification engineer to join the FPGA Business Unit and help verify next‑generation, secure, low‑power FPGA devices.

You will design and maintain UVM test benches, perform RTL and post‑silicon verification, collaborate with architecture, design, and emulation teams, and mentor junior engineers while advancing AI/ML‑based verification methodologies.