A complete application in a minute — tailored resume and cover letter, ready to send.
Get past ATS filters
Job summary
A semiconductor innovator in Dallas is looking for a verification engineer with over 5 years of mixed-signal verification experience. This role involves behavioral modeling and running dynamic verification for advanced DSP-based chips. Candidates should demonstrate strong coding skills in Verilog/SystemVerilog and familiarity with Cadence tools. Join a rapidly scaling startup focused on AI-driven connectivity.
Qualifications
5+ years of mixed-signal verification experience.
Strong background in Behavioral Modelling for analog-to-digital verification.
Basic understanding of analog design fundamentals.
Responsibilities
Perform behavioral modeling of analog designs.
Conduct mixed-signal dynamic verification using chip-level tools.
Write, simulate, and debug Verilog/SystemVerilog code.
Collaborate with engineering teams to validate designs.
Present verification results and maintain coverage metrics.
Skills
Mixed-signal verification
Behavioral Modeling
Verilog/SystemVerilog
Analog design fundamentals
Communication skills
Tools
Cadence Virtuoso
Synopsys verification tools
UVM
Job description
A semiconductor innovator in Dallas is looking for a verification engineer with over 5 years of mixed-signal verification experience. This role involves behavioral modeling and running dynamic verification for advanced DSP-based chips. Candidates should demonstrate strong coding skills in Verilog/SystemVerilog and familiarity with Cadence tools. Join a rapidly scaling startup focused on AI-driven connectivity.