Senior Verification Engineer - Mixed-Signal ASICs

Cirrus Logic; Chandler (AZ); Presencial; USD 100 000 - 130 000; Tempo integral

Resumo da oferta

Cirrus Logic is seeking a skilled silicon design verification engineer to join its team in Chandler, Arizona. You will collaborate with digital and analog designers to enhance verification methodologies and contribute to mixed-signal IC development.

This position requires at least 5 years of experience in silicon design or verification, alongside an MS or PhD in Electrical Engineering or related fields. Join a diverse team that values innovative solutions and personal growth.

Qualificações

• 5+ years of experience in silicon design or verification.
• Strong background with HDLs and HVLs.

Responsabilidades

• Perform verification planning.
• Testbench development using UVM methodologies.
• Implement functional verification of mixed-signal ASICs.
• Failure analysis and resolution.
• Digital/mixed-signal modeling.
• Develop directed/constraint-random test generation.

Conhecimentos

HDLs (e.g. Verilog, VHDL)

HVLs (e.g. SystemVerilog/UVM)

Silicon design verification

Mentoring junior engineers

Formação académica

MS or PhD in Electrical Engineering or Computer Engineering

Descrição da oferta de emprego

Cirrus Logic is seeking a skilled silicon design verification engineer to join its team in Chandler, Arizona. You will collaborate with digital and analog designers to enhance verification methodologies and contribute to mixed-signal IC development.

This position requires at least 5 years of experience in silicon design or verification, alongside an MS or PhD in Electrical Engineering or related fields. Join a diverse team that values innovative solutions and personal growth.