Job summary
A leading technology company in Arizona is looking for a Design Verification Engineer to join its silicon design verification team. The ideal candidate will have extensive experience in ASIC verification, specifically with mixed-signal designs. Responsibilities include developing verification plans, performing functional verifications, and implementing UVM-based testbenches. A Bachelor's, Master's, or PhD in Electrical or Computer Engineering is required, along with significant industry experience and strong skills in Verilog and SystemVerilog. This role offers opportunities for collaboration and process improvement.
Qualifications
- Bachelor’s with 7+ years, Master’s with 5+ years, PhD with 3+ years of relevant experience.
- Significant industry experience in silicon design or ASIC verification.
- Hands-on experience with regression execution and debug.
Responsibilities
- Develop comprehensive verification plans aligned with design and system requirements.
- Perform functional verification of custom mixed-signal ASICs at block and chip level.
- Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers.
Skills
Silicon design and/or ASIC verification
HDLs: Verilog and/or VHDL
HVLs: SystemVerilog with UVM (or OVM/AVM/Vera)
Digital design principles
Testbench architecture and stimulus generation
Coverage analysis
Education
Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field