Senior Mixed-Signal Verification Engineer

Cirrus Logic; Chandler (AZ); On-site; USD 90,000 - 130,000; Full time

Job summary

Cirrus Logic in Chandler, Arizona is seeking a Silicon Design Verification Engineer to join their team. You will work closely with digital and analog designers, participating in all aspects of verification for mixed-signal IC developments.

The ideal candidate will have an MS or PhD in engineering, a strong background in HDLs and HVLs, and at least 5 years of relevant experience. Cirrus Logic values an inclusive culture and offers a collaborative work environment.

Qualifications

• At least 5+ years of experience in silicon design or verification.
• Strong background with HDLs and HVLs is essential.
• Ability to mentor junior engineers in verification methodology.

Responsibilities

• Perform verification planning.
• Testbench development using UVM methodologies.
• Implement functional verification of mixed-signal ASICs.
• Failure analysis and resolution.
• Digital/mixed-signal modeling.
• Develop directed/constraint-random test generation.
• Regression debug support.

Skills

HDLs (Verilog, VHDL)

HVLs (SystemVerilog/UVM, OVM, AVM, Vera)

Silicon design or verification experience

Education

MS or PhD in Electrical Engineering or Computer Engineering

Job description

Cirrus Logic in Chandler, Arizona is seeking a Silicon Design Verification Engineer to join their team. You will work closely with digital and analog designers, participating in all aspects of verification for mixed-signal IC developments.

The ideal candidate will have an MS or PhD in engineering, a strong background in HDLs and HVLs, and at least 5 years of relevant experience. Cirrus Logic values an inclusive culture and offers a collaborative work environment.