Remote Senior Verification Architect - ASIC/FPGA

Fidus Systems; United States; Remote; USD 150,000 - 190,000; Full time

Benefits offered by this job

Medical, dental, vision

401(k) matching

Profit-sharing bonus

Supplementary benefits

Job summary

Fidus is seeking an experienced Verification Designer to own block- and system-level verification for ASIC/FPGA designs, building UVM, formal, and assertion-based environments and driving coverage closure, often working directly with clients on verification strategy.

You bring 8+ years of verification leadership, strong SystemVerilog/UVM fluency, CRV knowledge, and scripting skills to automate tasks across cross-functional teams.

Qualifications

• 8+ years of ASIC/FPGA verification experience with leadership.
• Strong SystemVerilog and UVM fluency, CRV techniques.
• Familiarity with verification metrics, coverage, and formal methods.

Responsibilities

• Own block- and system-level verification of ASIC/FPGA designs from test plan to closure.
• Design and implement UVM, formal, and assertion-based environments; apply CRV.
• Develop models and tests to achieve functional coverage goals; track metrics to closure.
• Debug and troubleshoot simulation/regression failures with cross-functional teams.
• Automate verification tasks using scripting languages (Python/Perl/Tcl).
• Plan and report status on multiple verification activities as a lead.
• Collaborate with clients on verification strategy and support.

Skills

ASIC/FPGA verification

SystemVerilog/UVM

CRV techniques

Functional coverage/Assertions

Industry protocols

Scripting (Python/Perl/Tcl)

Debugging/Problem solving

Client-facing

Education

Bachelor's or Master's in Electrical/Computer Engineering or related field

Job description

Fidus is seeking an experienced Verification Designer to own block- and system-level verification for ASIC/FPGA designs, building UVM, formal, and assertion-based environments and driving coverage closure, often working directly with clients on verification strategy.

You bring 8+ years of verification leadership, strong SystemVerilog/UVM fluency, CRV knowledge, and scripting skills to automate tasks across cross-functional teams.