Senior UVM Verification Engineer (Contract) - Sunnyvale

Cystems Logic Inc; Sunnyvale (CA); On-site; USD 96,000 - 165,000; Part time

Job summary

Cystems Logic Inc. in Sunnyvale, CA is seeking a Design Verification Engineer (UVM) to develop and maintain UVM-based verification environments for complex semiconductor designs.

The role emphasizes hands-on SystemVerilog, constrained-random verification, and SVAs, with close collaboration with RTL teams to ensure thorough functional and coverage verification. The candidate will drive verification planning, create test plans, and automate tasks using scripting languages.

Qualifications

• Hands-on experience in UVM-based verification environments.
• Excellent knowledge of SystemVerilog.
• Experience developing reusable UVM testbenches from scratch.
• Strong understanding of OOP concepts and constrained-random verification.
• Experience with UVM sequences, drivers, monitors, agents, and scoreboards.
• Hands-on experience with SystemVerilog Assertions (SVA).
• Knowledge of functional coverage and code coverage.
• Experience with simulation and debugging tools such as Synopsys VCS and Cadence Xcelium.

Responsibilities

• Develop and maintain reusable UVM-based verification environments.
• Create and implement test plans, test scenarios, and verification strategies.
• Develop constrained-random and directed test cases using SystemVerilog.
• Build and maintain UVM components, including agents, drivers, monitors, sequencers, and scoreboards.
• Develop assertions using SystemVerilog Assertions (SVA).
• Perform functional, code, and assertion coverage analysis.
• Debug simulation failures and identify design or testbench issues.
• Work closely with RTL designers and architecture teams to understand design specifications.
• Drive functional coverage closure and achieve verification sign-off.
• Participate in design reviews, verification planning, and regression analysis.
• Automate verification tasks using scripting languages such as Python, Perl, or Shell.

Skills

UVM-based verification

SystemVerilog

Constrained-random verification

Testbench development

SystemVerilog Assertions (SVA)

Debugging and coverage analysis

Tools

Synopsys VCS

Cadence Xcelium

Job description

Cystems Logic Inc. in Sunnyvale, CA is seeking a Design Verification Engineer (UVM) to develop and maintain UVM-based verification environments for complex semiconductor designs.

The role emphasizes hands-on SystemVerilog, constrained-random verification, and SVAs, with close collaboration with RTL teams to ensure thorough functional and coverage verification. The candidate will drive verification planning, create test plans, and automate tasks using scripting languages.