Senior Verification Engineer: SystemVerilog/UVM for SoC

iFlow Inc.; Santa Clara (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

iFlow Inc. in Santa Clara, CA is seeking a Design Verification Engineer with 8–15 years of experience to join a long-term role. You will develop verification environments, perform coverage analysis, and work closely with RTL designers to debug simulation failures, ensuring high-quality designs across domains.

The ideal candidate demonstrates strong SystemVerilog and UVM skills and a hands-on approach to debugging and verification workflow in a fast-paced hardware environment.

Qualifications

• 8–15 years of relevant design verification experience.
• Strong SystemVerilog and UVM proficiency.
• Experience debugging simulations and identifying design issues.
• Ability to develop verification environments for testing.

Responsibilities

• Develop verification environments for testing.
• Perform coverage analysis to ensure thorough verification.
• Collaborate with RTL designers to debug simulation failures.
• Ensure design quality across multiple domains.

Skills

SystemVerilog

UVM

Debugging

Coverage analysis

Job description

iFlow Inc. is seeking a Design Verification Engineer based in Santa Clara, CA, for a long-term position. The successful candidate will possess 8-15 years of experience, showcasing a strong proficiency in SystemVerilog and UVM, alongside debugging skills.

Key responsibilities include developing verification environments for testing, performing coverage analysis, and collaborating with RTL designers to debug simulation failures while ensuring design quality across various domains.