Staff IC Verification Engineer: UVM & SystemVerilog Expert

Broadcom, Inc.; Fort Collins (CO); On-site; USD 110,000 - 176,000; Full time

Benefits offered by this job

Medical plan

Dental plan

Vision plan

401(k) with company match

Employee Stock Purchase Program

Employee Assistance Program

Paid holidays

Paid time off

Job summary

Broadcom, Inc. in Fort Collins, CO, seeks an experienced verification engineer to develop verification environments with SystemVerilog and UVM, and to design verification components such as sequences, agents, and scoreboards.

You will implement coverage and assertions and develop random and directed tests to close coverage gaps. The role requires deep HDL knowledge, experience with constrained random environments, and proficiency in C++/Java.

Qualifications

• Verified expertise in HDL languages Verilog/VHDL and SystemVerilog.
• Experience with constrained random verification environments (UVM/OVM/VMM).
• Proficiency with HDL simulators and debugging techniques.
• Strong OO programming knowledge (C++, Java) and experience.
• Ability to think critically and lead complex engineering problems.
• Independent contributor who can work in a matrix organization.
• US work authorization is required; no immigration sponsorship.

Responsibilities

• Develop verification environments using SystemVerilog and UVM.
• Design verification classes such as UVM sequences, agents, scoreboards, and models.
• Implement coverage and assertions in SystemVerilog.
• Create random and directed test cases to close coverage gaps.
• Analyze and debug simulation failures and coverage results.

Skills

Verilog/SystemVerilog

UVM/OVM/VMM

HDL simulators

C++

Java

Communication skills

Leadership

Independent thinking

Education

Bachelor's in EE/CE/CS with 8+ years related experience; or Masters in EE/CE/CS with 6+ years related experience

Tools

ModelSim

VCS

Job description

Broadcom, Inc. in Fort Collins, CO, seeks an experienced verification engineer to develop verification environments with SystemVerilog and UVM, and to design verification components such as sequences, agents, and scoreboards.

You will implement coverage and assertions and develop random and directed tests to close coverage gaps. The role requires deep HDL knowledge, experience with constrained random environments, and proficiency in C++/Java.