Senior UVM Design Verification Engineer – SoC Timing & Validation

Socket.dev; San Jose (CA); On-site; USD 101,000 - 162,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity awards

Broadcom benefits package

Job summary

Broadcom in San Jose, CA seeks an experienced design verification engineer with a proven track record in setting up UVM-based testbenches for large designs. The role spans from initial specification through timing closure and hand-off to physical design, with strong cross‑functional collaboration.

Requirements include a BSEE and 5+ years in SoC integration and test bench setup. The package features a discretionary annual bonus, equity awards, and Broadcom's comprehensive benefits.

Qualifications

• The ideal candidate has a proven track record of working on setting up testbenches for Design Verification using UVM on large designs.
• 5+ years of industry experience with a focus on SoC integration, UVM test bench setup and design debug.

Responsibilities

• Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off
• Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule
• High proficiency in UVM

Skills

UVM

Education

BSEE

MSEE/PhD preferred

Job description

Broadcom in San Jose, CA seeks an experienced design verification engineer with a proven track record in setting up UVM-based testbenches for large designs. The role spans from initial specification through timing closure and hand-off to physical design, with strong cross‑functional collaboration.

Requirements include a BSEE and 5+ years in SoC integration and test bench setup. The package features a discretionary annual bonus, equity awards, and Broadcom's comprehensive benefits.