IC Verification Engineer (SystemVerilog/UVM) - Equity

Broadcom; San Jose (CA); On-site; USD 108,000 - 173,000; Full time

Benefits offered by this job

401(k) with company match

Employee stock purchase program (ESPP)

Paid time off

Job summary

Broadcom is seeking an experienced verification engineer to verify complex switch designs. You will develop SystemVerilog testbenches, create test plans, and run tests at both block and chip levels. The role includes creating ATE vectors and C-based diagnostic tests for silicon validation.

The ideal candidate has a Master’s degree in a relevant field and at least six years of DV experience, with strong scripting skills and knowledge of UVM. On-site work in San Jose, CA is expected.

Qualifications

• Master’s degree in Electrical and Electronic Engineering, Computer Science, or equivalent.
• Minimum 6 years of work experience in Design Verification.
• Strong knowledge of verification methods, tools, and environments.
• Proficiency in SystemVerilog and scripting languages.
• Knowledge of UVM methodology is preferable.
• Knowledge of networking and switching concepts is a plus.

Responsibilities

• Create SystemVerilog-based testbenches, checkers, and transactors for RTL and gate-level designs.
• Develop and execute test plans for verification.
• Build and run ATE testing vectors and C-based diagnostic tests on silicon.
• Collaborate with design and validation teams to ensure coverage.

Skills

SystemVerilog

UVM

Scripting

Education

Master’s degree in Electrical and Electronic Engineering, Computer Science, or equivalent

Tools

Testbenches

Job description

Broadcom is seeking an experienced verification engineer to verify complex switch designs. You will develop SystemVerilog testbenches, create test plans, and run tests at both block and chip levels. The role includes creating ATE vectors and C-based diagnostic tests for silicon validation.

The ideal candidate has a Master’s degree in a relevant field and at least six years of DV experience, with strong scripting skills and knowledge of UVM. On-site work in San Jose, CA is expected.