Senior Timing Analysis & Signoff Engineer

Cadence Design Systems; San Jose (CA); On-site; USD 127,000 - 237,000; Full time

Job summary

Cadence Design Systems in San Jose is seeking a Senior STA specialist to lead timing signoff campaigns and deliver robust timing solutions for advanced technology nodes. Ideal candidates will have extensive experience with Tempus Signoff, SDC constraints, OCv/SOCV concepts, and cross‑functional collaboration with R&D and customers to enable timing analysis and ECO flows.

Join Cadence to influence silicon success from design through signoff, with opportunities to travel to customer sites and

Qualifications

• 8+ years of experience in Static Timing Analysis.
• Ability to lead timing signoff campaigns with Cadence Tempus.
• Experience executing timing ECO flows and cross-team collaboration.
• Familiarity with Place & Route, Clock Tree, RC Extraction, UPF/CPF.
• Strong scripting skills in Perl, Tcl, or Python.

Responsibilities

• Perform Static timing analysis, glitch, and noise analysis using Tempus Signoff tool.
• Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, distributed and concurrent STA flows.
• Collaborate with R&D and customers to enable timing analysis and ECO flows for newer technologies.
• Perform timing correlation, tool feature benchmarking, constraints validation, spice analysis on various nodes and customer designs.
• Work on in-design timing ECO optimizations with basic knowledge of Place and Route, Clock Tree, RC Extraction and UPF/CPF concepts.
• Execute and lead Tempus timing signoff campaigns at existing and new customers.
• Automation of flows using scripting languages (Perl, Tcl, python).
• Deliver technical trainings and seminars within Cadence and customer sites.

Skills

Static timing analysis

Timing signoff campaigns

Scripting automation

Place & Route concepts

Clock Tree

RC Extraction

UPF/CPF concepts

Collaboration with R&D and customers

Tools

Tempus Signoff

Perl

Tcl

Python

Job description

Cadence Design Systems in San Jose is seeking a Senior STA specialist to lead timing signoff campaigns and deliver robust timing solutions for advanced technology nodes. Ideal candidates will have extensive experience with Tempus Signoff, SDC constraints, OCv/SOCV concepts, and cross‑functional collaboration with R&D and customers to enable timing analysis and ECO flows.

Join Cadence to influence silicon success from design through signoff, with opportunities to travel to customer sites and