Senior Application Architect — Timing Signoff & Innovation

Cadence; San Jose (CA); Sur place; USD 154 000 - 286 000; Plein temps

Avantages offerts par ce poste

Paid vacation & holidays

401(k) plan with employer match

Employee stock purchase plan

Medical, dental and vision plans

And more

Résumé du poste

Cadence in San Jose seeks an senior IC design and signoff leader to drive large-scale engagements and tool adoption across advanced nodes. You will guide teams, align R&D with real customer needs, and push innovative timing closure methodologies.

Ideal candidates have 15+ years in IC design/signoff, deep STA knowledge, and strong scripting skills. Expect executive collaboration, influential communication, and ongoing Cadence leadership representation.

Qualifications

• 15+ years of experience in IC design implementation and signoff.
• Deep expertise in digital design fundamentals, advanced node STA & ECOs (3nm and below).
• Core timing signoff expertise and hierarchical/3DIC design STA.
• Proven track record leading technical teams and executive-level customer success.
• Strong scripting skills in Tcl, Python, and Perl.
• Experience with Cadence tools (Tempus, Certus, QRC).

Responsabilités

• Lead technical engagements with customers and partners to drive adoption of Cadence signoff portfolio.
• Collaborate with R&D and Product Engineering to influence tool enhancements.
• Drive benchmarks, flow optimizations, and deployment of timing signoff and power/timing closure methodologies.
• Represent Cadence at industry forums and deliver technical talks to position Cadence as a market leader.

Connaissances

Scripting Tcl/Python/Perl

Leadership

Communication

Customer engagement

Formation

BS/MS in Electrical Engineering, Computer Engineering, or related field

Outils

Cadence Tempus

Cadence Certus

QRC

Description du poste

Cadence in San Jose seeks an senior IC design and signoff leader to drive large-scale engagements and tool adoption across advanced nodes. You will guide teams, align R&D with real customer needs, and push innovative timing closure methodologies.

Ideal candidates have 15+ years in IC design/signoff, deep STA knowledge, and strong scripting skills. Expect executive collaboration, influential communication, and ongoing Cadence leadership representation.