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Cadence seeks a senior design/verification engineer to join the HSV Engagement/Support Team in California. You will collaborate with customers, field AE teams and R&D to provide technical support for Palladium, Protium and Virtual Protocol products, addressing complex hardware and software challenges.
Requires MS-EE/CE with 8+ years in design/verification of digital designs or related support roles; strong HDL (Verilog, SystemVerilog, VHDL); Unix/Linux scripting; UVM is a plus.
Cadence seeks a senior design/verification engineer to join the HSV Engagement/Support Team in California. You will collaborate with customers, field AE teams and R&D to provide technical support for Palladium, Protium and Virtual Protocol products, addressing complex hardware and software challenges.
Requires MS-EE/CE with 8+ years in design/verification of digital designs or related support roles; strong HDL (Verilog, SystemVerilog, VHDL); Unix/Linux scripting; UVM is a plus.