Senior Principal Design Engineer - Emulation & FPGA

Cadence Design Systems

San Jose (CA)

Hybrid

USD 154,000 - 286,000

Full time

14 days+

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Job summary

Cadence Design Systems in San Jose, CA, seeks a Senior Principal Design Engineer for Palladium & Protium Customer Support. You will work directly with leading semiconductor and systems companies to deploy Cadence hardware emulation and FPGA prototyping, bridging customers with AE, PE, and R&D teams to deliver advanced verification solutions.

Responsibilities include enabling customers, defining emulation requirements, driving FW/FPGA system solutions, debugging across hardware and software, and

Qualifications

  • BS with 10+ years or MS with 7+ years in a relevant field.
  • Strong fundamentals in digital design and system-level verification.
  • Experience with HDL (SystemVerilog/Verilog) and/or C/C++.
  • Understanding of high-speed interfaces and memory protocols.
  • Excellent communication and ability to work across teams.

Responsibilities

  • Collaborate with customers and engineering teams to enable Palladium/Protium deployments.
  • Define and develop customer-specific emulation and prototyping requirements.
  • Drive advanced FW/FPGA system solutions and verification methodologies.
  • Triage and debug issues across hardware/software boundaries.
  • Create technical presentations and product demonstrations.

Skills

Digital design
System-level verification
SystemVerilog/Verilog
C/C++
Emulation/FPGA
Interconnect protocols
Debugging with waveforms
Cross-functional collaboration
Communication skills

Education

Bachelor's degree in a relevant field
Master's degree in a relevant field

Tools

Waveform analyzers
HDL simulators
Protocol analyzers

Job description

Cadence Design Systems in San Jose, CA, seeks a Senior Principal Design Engineer for Palladium & Protium Customer Support. You will work directly with leading semiconductor and systems companies to deploy Cadence hardware emulation and FPGA prototyping, bridging customers with AE, PE, and R&D teams to deliver advanced verification solutions.

Responsibilities include enabling customers, defining emulation requirements, driving FW/FPGA system solutions, debugging across hardware and software, and

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