Senior Substrate IC Layout Engineer – >50GHz, 700W Power

Etched; San Jose (CA); On-site; USD 200,000 - 280,000; Full time

Benefits offered by this job

Medical coverage

Housing subsidy

Relocation support

Wellness benefits

Daily meals

Compute budget

Job summary

Etched is seeking a Substrate IC Package Layout Design Engineer in San Jose to lead end‑to‑end substrate layouts for high‑performance AI processors. You will push the envelope on >50GHz signaling and robust >700W power delivery while collaborating with silicon, signal integrity, and manufacturing teams.

You’ll apply CoWoS interposer expertise, perform DRC/LVS, and drive design documentation. This role is hands‑on and cross‑functional in a fast‑paced environment.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field
• 10+ years IC substrate layout design for high-performance processors/ accelerators
• Experience with large substrates (>50mm) and dense layouts
• Experience with high-power (700W+) package designs
• High-speed signaling design (>50GHz) and addressing SI/PI challenges
• CoWoS interposer design experience
• Allegro Package Designer expertise
• Strong analytical and cross-functional collaboration skills

Responsibilities

• IC Substrate Layout Design for complex AI processors and accelerators
• Lead design of large (>50mm) substrates with high pin counts
• Ensure robust power delivery for >700W silicon solutions
• Develop high-speed routing for >50GHz signaling
• Collaborate with SI/PI engineers to satisfy requirements
• Optimize CoWoS interposer designs for performance
• Work with chip design, packaging, and manufacturing teams
• Perform DRC and LVS verification for substrates
• Create design documentation and guidelines
• Support design reviews and mentor juniors

Job description

Etched is seeking a Substrate IC Package Layout Design Engineer in San Jose to lead end‑to‑end substrate layouts for high‑performance AI processors. You will push the envelope on >50GHz signaling and robust >700W power delivery while collaborating with silicon, signal integrity, and manufacturing teams.

You’ll apply CoWoS interposer expertise, perform DRC/LVS, and drive design documentation. This role is hands‑on and cross‑functional in a fast‑paced environment.