A leading semiconductor company in San Jose is looking for an IC Substrate and Package Layout Engineer. The ideal candidate will design and layout advanced substrates and IC packages, collaborating with cross-functional teams to ensure high-performance results. This role requires expertise with Cadence layout tools and offers a competitive salary range of $141,300 - $226,000 along with a comprehensive benefits package, including bonuses and equity grants.
Qualifications
12 years of related experience with a bachelor's degree.
10+ years of experience with a master's degree.
7+ years of experience with a PhD.
Responsibilities
Design and layout advanced substrates and IC packages.
Develop and utilize script-based layout tools.
Collaborate with design and verification teams.
Skills
Expertise with Cadence layout tools
Knowledge of multilayer high speed RF design
Deep understanding of package/substrate manufacturing processes
Experience with DRC and LVS checking
Collaboration with cross-functional teams
Education
Bachelor's degree in Material Science/Electrical/Computer/Mechanical Engineering
A leading semiconductor company in San Jose is looking for an IC Substrate and Package Layout Engineer. The ideal candidate will design and layout advanced substrates and IC packages, collaborating with cross-functional teams to ensure high-performance results. This role requires expertise with Cadence layout tools and offers a competitive salary range of $141,300 - $226,000 along with a comprehensive benefits package, including bonuses and equity grants.