Senior Staff IC Design Engineer – SOC & IP Integration

Anysilicon; Santa Clara (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Marvell is seeking a seasoned SoC design engineer to lead integration of internal and external IP blocks within the SOC team in Santa Clara. You will own portions of the SOC from inception to tape-out, collaborate on floorplanning, and drive timing closure using state-of-the-art EDA tools.

The role requires strong SystemVerilog RTL skills, experience with clock/reset, CDC, and timing constraints, and familiarity with ARM protocols and interconnect architectures.

Qualifications

• Bachelor’s degree in Computer Engineering or Electrical Engineering with 5+ years of experience, or a Master/PhD with 3+ years.
• Experience taping out complex SoCs and post-silicon debugging.
• Strong SystemVerilog RTL design skills.
• Experience with clock/reset design, CDC, and timing constraints.
• Understanding of front-end RTL decisions and their impact on physical implementation.
• Familiarity with ARM protocols and SoC interconnect architectures.

Responsibilities

• Integrate internal and external IP blocks at the chip level with the SOC Integration team.
• Take ownership of a portion of SOC design from initial stages to completion.
• Collaborate on floorplan and manage interconnection of IP blocks.
• Conduct static checks and assist with subsystem and chip-level verification efforts.
• Drive to timing closure and collaborate with cross-disciplinary teams to ensure high-quality product tape-out.
• Utilize industry and internal EDA tools for functional simulations, gate-level simulations, and code quality checks.
• Lead design efforts for internally developed processor IP blocks to meet architectural needs.
• Work closely with verification and implementation teams to fulfill product requirements.
• Deliver micro-architectural specifications and participate in automation tool development to enhance workflows.
• Leverage next-generation AI tools to improve existing processes.

Skills

SystemVerilog

RTL design

Python

Tcl

Communication

Problem-solving

Analytical thinking

Education

Bachelor’s degree in Computer/Electrical Engineering

Master’s/PhD in related field

Tools

ARM protocols (APB/AHB/AXI/CHI)

EDA tools

Job description

Marvell is seeking a seasoned SoC design engineer to lead integration of internal and external IP blocks within the SOC team in Santa Clara. You will own portions of the SOC from inception to tape-out, collaborate on floorplanning, and drive timing closure using state-of-the-art EDA tools.

The role requires strong SystemVerilog RTL skills, experience with clock/reset, CDC, and timing constraints, and familiarity with ARM protocols and interconnect architectures.