Principal SOC Integration Engineer — Onsite with Flexible Work

Samsung Semiconductor; San Jose (CA); On-site; USD 219,000 - 351,000; Full time

Benefits offered by this job

Medical/Dental/Vision/401k

Inclusive rewards plan

4+ weeks paid time off

Job summary

Samsung Semiconductor is seeking a Principal Engineer, SOC Integration for our San Jose, CA location. You will lead the integration of SOCs with multiple high-speed interfaces and collaborate with architects, verification engineers, and physical designers to ensure a robust, scalable memory and storage solution.

The role requires deep expertise in ASIC design flow, SoC synthesis, timing analysis, and experience with AMBA, ARM cores, and UCIe/IPs.

Qualifications

• BS/ MS with required years in engineering or CS.
• Hands-on ASIC design flow experience from design to tape-out.
• Experience with UCIe, CPU, Ethernet, and DDR IPs.

Responsibilities

• Own the integration of SoCs with multiple high speed interfaces.
• Review 3rd party IPs including ARM cores, DDR controller, and UCIe PHY.
• Integrate third party IPs with system bus, peripherals and CPU cores.
• Collaborate with architects and verification engineers to ensure sound SoC design.
• Coordinate with physical designers on timing constraints, synthesis, DFT, and static timing analysis.

Skills

ASIC design flow

SoC integration

ARM cores

UCIe IPs

DDR interfaces

AMBA bus fabric

Synthesis & timing

Lint & CDC checks

Problem solving

Teamwork

Education

BS in Computer/Electrical Engineering or Computer Science

MS with 18+ years of experience

Job description

Samsung Semiconductor is seeking a Principal Engineer, SOC Integration for our San Jose, CA location. You will lead the integration of SOCs with multiple high-speed interfaces and collaborate with architects, verification engineers, and physical designers to ensure a robust, scalable memory and storage solution.

The role requires deep expertise in ASIC design flow, SoC synthesis, timing analysis, and experience with AMBA, ARM cores, and UCIe/IPs.