Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Anysilicon; Irvine, Northern (CA, KY); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Marvell is seeking a Senior Staff Engineer to lead ASIC/VLSI synthesis and design in Irvine, CA. You will develop timing constraints, collaborate across RTL, Architecture, DFT, and Analog teams, and own Front-End tasks including Synthesis, UPF, and ECOs to meet power, performance and area targets.

You will drive Physical Aware Synthesis with Fusion Compiler, automate flows with Tcl/Python, and ensureNetlist handoff readiness for PD. Strong scripting and EDA tool experience are required.

Qualifications

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 5–10 years of experience.
• Master’s degree or PhD with 3–5 years of experience in ASIC/SOC design is a plus.
• Experience in ASIC implementation from RTL to GDSII and familiarity with timing constraints.

Responsibilities

• Develop and validate timing constraints for intricate SoC designs.
• Collaborate with Architecture, RTL, DFT, and Analog teams to analyze timing complexities and develop consolidated timing modes and constraints.
• Own and contribute to Front-End Implementation tasks such as Synthesis, UPF development, LEC, and Functional ECOs.
• Analyze trade-offs between power, performance, and area goals to drive chip implementation flows.
• Perform Physical Aware Synthesis using Fusion Compiler.
• Resolve tool issues independently or with EDA tool vendors.
• Automate Front End Flows and processes using Tcl or Python.
• Ensure compliance with Netlist Handoff checklists for delivery to PD.
• Document best practices and lessons learned for continuous improvement.

Skills

Timing constraints

Synthesis

STA methodologies

Tcl scripting

Python scripting

UPF development

Conformal ECO

Front End Synthesis

Education

Bachelor's degree in CS/EE

Master's or PhD in related field

Tools

Fusion Compiler

Conformal ECO

STA tools

EDA tools

Job description

Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Marvell is a leading provider of semiconductor solutions that form the backbone of data infrastructure across various sectors, including enterprise, cloud, AI, and carrier architectures. The company is focused on innovative technology that drives meaningful change and enhances the efficiency of data processing, particularly in the realm of Generative AI and accelerated computing. Marvell's Photonic Fabric™ technology represents a significant advancement in interconnect solutions, offering high bandwidth and low latency for AI accelerators and GPUs, thereby optimizing performance and reducing costs for hyperscalers.

Responsibilities:

• Develop and validate timing constraints for intricate SoC designs.
• Collaborate with Architecture, RTL, DFT, and Analog teams to analyze timing complexities and develop consolidated timing modes and constraints.
• Own and contribute to Front-End Implementation tasks such as Synthesis, UPF development, Logical Equivalence Checks (LEC), and Functional ECOs.
• Analyze trade-offs between power, performance, and area goals to drive chip implementation flows.
• Perform Physical Aware Synthesis using industry-standard tools like Fusion Compiler.
• Resolve tool issues independently or with EDA tool vendors.
• Automate Front End Flows and processes using scripting languages like Tcl or Python.
• Ensure compliance with Netlist Handoff checklists for delivery to PD.
• Document best practices and lessons learned for continuous improvement.

Qualifications:

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 5-10 years of experience, or a Master’s/PhD with 3-5 years of experience.
• Minimum of 5 years of industry experience in ASIC implementation and synthesis.
• Strong understanding of ASIC design flows from RTL to GDSII.
• Knowledge and hands-on experience with synthesis and STA methodologies.
• Proficiency in using synthesis tools, STA tools, and scripting languages (e.g., Tcl, Perl).
• Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5.
• Strong understanding of timing constraint development for hierarchical designs.
• Experience with functional ECOs using industry-standard tools and flows like Conformal ECO.
• Familiarity with UPF development for blocks and SoCs.

Skills:

• Expertise in timing constraints development and synthesis methodologies.
• Proficient in scripting languages such as Tcl and Python.
• Strong analytical skills for timing analysis and optimization.
• Ability to collaborate effectively with cross-functional teams.
• Experience with Physical Aware Synthesis and EDA tools.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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• ASIC Design Services
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