Senior SoC Design Engineer: IP Integration & Automation

Cadence Design Systems; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Cadence Design Systems is seeking an experienced digital design engineer to design and integrate IPs for complex SoCs. You will use Verilog/SystemVerilog, run Lint/CDC checks, and create synthesis constraints for PPA optimization.

You will support verification and physical teams, automate repetitive tasks, and collaborate across multiple disciplines to deliver high-quality designs. Applicants should have 8–12 years of hands-on digital design experience, AMBA/ARM IP familiarity, and strong

Qualifications

• B.E./B.Tech./M.Tech in Electrical Engineering is required.
• 8–12 years of experience as a digital design engineer.
• Strong knowledge of digital design fundamentals and Verilog/SystemVerilog (SV).
• Experience with Lint/CDC tools and setting up flows from scratch.

Responsibilities

• Design and integration of IPs in SoC based on high-level architectural specifications from customers.
• Perform Lint/CDC checks on the design for quality assurance and resolve related issues.
• Create synthesis constraints for the design at the IP and SoC level and perform basic synthesis for PPA optimization.
• Create detailed Microarchitectural Specification documents for the design.
• Provide support to the verification team for test plan creation, coverage analysis, and feature debugging.
• Provide support to the physical design team as needed for design implementation.
• Implement innovative solutions to automate repetitive tasks.
• Collaborate within and across teams for effective project execution.

Skills

Digital design

Verilog/SystemVerilog

Lint/CDC flows

Synthesis constraints

STA timing analysis

AMBA protocols

PCIe/Ethernet/DDR

Python/Perl/Tcl

Strong communication

Education

B.E./B.Tech./M.Tech in Electrical Engineering

Tools

Xcelium

Verisium

Synthesis tools

Job description

Cadence Design Systems is seeking an experienced digital design engineer to design and integrate IPs for complex SoCs. You will use Verilog/SystemVerilog, run Lint/CDC checks, and create synthesis constraints for PPA optimization.

You will support verification and physical teams, automate repetitive tasks, and collaborate across multiple disciplines to deliver high-quality designs. Applicants should have 8–12 years of hands-on digital design experience, AMBA/ARM IP familiarity, and strong