Senior ASIC/VLSI Synthesis Engineer: FrontEnd Timing Expert

Anysilicon; Irvine, Northern (CA, KY); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Marvell is seeking a Senior Staff Engineer to lead ASIC/VLSI synthesis and design in Irvine, CA. You will develop timing constraints, collaborate across RTL, Architecture, DFT, and Analog teams, and own Front-End tasks including Synthesis, UPF, and ECOs to meet power, performance and area targets.

You will drive Physical Aware Synthesis with Fusion Compiler, automate flows with Tcl/Python, and ensureNetlist handoff readiness for PD. Strong scripting and EDA tool experience are required.

Qualifications

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 5–10 years of experience.
• Master’s degree or PhD with 3–5 years of experience in ASIC/SOC design is a plus.
• Experience in ASIC implementation from RTL to GDSII and familiarity with timing constraints.

Responsibilities

• Develop and validate timing constraints for intricate SoC designs.
• Collaborate with Architecture, RTL, DFT, and Analog teams to analyze timing complexities and develop consolidated timing modes and constraints.
• Own and contribute to Front-End Implementation tasks such as Synthesis, UPF development, LEC, and Functional ECOs.
• Analyze trade-offs between power, performance, and area goals to drive chip implementation flows.
• Perform Physical Aware Synthesis using Fusion Compiler.
• Resolve tool issues independently or with EDA tool vendors.
• Automate Front End Flows and processes using Tcl or Python.
• Ensure compliance with Netlist Handoff checklists for delivery to PD.
• Document best practices and lessons learned for continuous improvement.

Skills

Timing constraints

Synthesis

STA methodologies

Tcl scripting

Python scripting

UPF development

Conformal ECO

Front End Synthesis

Education

Bachelor's degree in CS/EE

Master's or PhD in related field

Tools

Fusion Compiler

Conformal ECO

STA tools

EDA tools

Job description

Marvell is seeking a Senior Staff Engineer to lead ASIC/VLSI synthesis and design in Irvine, CA. You will develop timing constraints, collaborate across RTL, Architecture, DFT, and Analog teams, and own Front-End tasks including Synthesis, UPF, and ECOs to meet power, performance and area targets.

You will drive Physical Aware Synthesis with Fusion Compiler, automate flows with Tcl/Python, and ensureNetlist handoff readiness for PD. Strong scripting and EDA tool experience are required.