Senior STA Signoff & Timing Methodology Engineer

NVIDIA AI; Santa Clara (TX); On-site; USD 196,000 - 311,000; Full time

Job summary

NVIDIA is seeking a seasoned ASIC timing engineer to drive timing-signoff strategies and robust silicon performance. You will run SPICE simulations, develop STA/PNR flows, and collaborate across physical design and timing teams to push aging, self-heating and IR-drop challenges to solutions.

The role requires a strong foundation in device physics, RC extraction, and modern low-power techniques, with deep experience in PrimeTime, ICC2, RedHawk, and Tempus. Join NVIDIA’s high-impact environment.

Qualifications

• MS in Electrical or Computer Engineering or equivalent with 8 years of ASIC timing experience.
• Strong understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations.
• Proven foundation in the mathematics and physics underlying electrical design.
• Experience with low-power techniques including multi-Vt design, clock gating, power gating, activity-based power analysis, DVFS, and CDC.

Responsibilities

• Run large-scale SPICE simulations and STA experiments to model the impact of advanced technologies on chip timing.
• Develop STA and PNR flows and recommendations addressing aging, self-heating, thermal effects, IR drop, electromigration, and other advanced-node effects.
• Collaborate with technology leads, physical-design engineers, and timing engineers to define and deploy timing-signoff strategies for silicon performance.
• Develop tools and methodologies that improve design performance, predictability, and silicon reliability beyond standard EDA tools.
• Work across STA, constraints, and timing and power optimization.
• Perform extensive data analysis using Python, JMP, or similar tools to improve STA-to-silicon correlation.

Skills

ASIC design

Timing analysis

RC extraction

Device physics

STA methodologies

EDA tools

Clocking techniques

Power analysis

Crosstalk

DVFS

Education

MS in Electrical or Computer Engineering

Tools

PrimeTime

ICC2

RedHawk

Tempus

Job description

NVIDIA is seeking a seasoned ASIC timing engineer to drive timing-signoff strategies and robust silicon performance. You will run SPICE simulations, develop STA/PNR flows, and collaborate across physical design and timing teams to push aging, self-heating and IR-drop challenges to solutions.

The role requires a strong foundation in device physics, RC extraction, and modern low-power techniques, with deep experience in PrimeTime, ICC2, RedHawk, and Tempus. Join NVIDIA’s high-impact environment.