Senior ASIC Timing & Physical Design Engineer - Equity

NVIDIA AI; Westford (MA); On-site; USD 180,000 - 310,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior ASIC Timing Design Engineer to join the Networking Silicon engineering team. You will drive timing design for high-speed DPUs and SoCs, optimizing constraints and convergence while supporting RTL-to-GDS2 flows and ECO implementations.

The role requires hands-on STA experience, strong ECO capabilities, and expertise with industry standard EDA tools. Equity and benefits are included, with a base salary reflecting Level 4/5 bands.

Qualifications

• Hands-on experience in full-chip STA, timing constraints generation and management.

Responsibilities

• Drive physical design and timing of high-frequency DPUs and SoCs at block, chiplet or full chip level.
• Analyze and optimize design constraints and synthesis parameters for performance, power, and area.
• Lead frontend and backend implementation from RTL to GDS2, including synthesis, EC, floorplanning, timing, and ECOs.

Skills

Synthesis and Timing

STA/Timing Convergence

ECOs debugging

DFT timing closure

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

Synopsys PrimeTime

Cadence Tempus

Python

Tcl

Make

Job description

NVIDIA is seeking a Senior ASIC Timing Design Engineer to join the Networking Silicon engineering team. You will drive timing design for high-speed DPUs and SoCs, optimizing constraints and convergence while supporting RTL-to-GDS2 flows and ECO implementations.

The role requires hands-on STA experience, strong ECO capabilities, and expertise with industry standard EDA tools. Equity and benefits are included, with a base salary reflecting Level 4/5 bands.