Senior STA Signoff Methodology Engineer

NVIDIA AI; Santa Clara (TX); On-site; USD 196,000 - 311,000; Full time

Job summary

NVIDIA is seeking a seasoned ASIC timing engineer to drive timing-signoff strategies and robust silicon performance. You will run SPICE simulations, develop STA/PNR flows, and collaborate across physical design and timing teams to push aging, self-heating and IR-drop challenges to solutions.

The role requires a strong foundation in device physics, RC extraction, and modern low-power techniques, with deep experience in PrimeTime, ICC2, RedHawk, and Tempus. Join NVIDIA’s high-impact environment.

Qualifications

• MS in Electrical or Computer Engineering or equivalent with 8 years of ASIC timing experience.
• Strong understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations.
• Proven foundation in the mathematics and physics underlying electrical design.
• Experience with low-power techniques including multi-Vt design, clock gating, power gating, activity-based power analysis, DVFS, and CDC.

Responsibilities

• Run large-scale SPICE simulations and STA experiments to model the impact of advanced technologies on chip timing.
• Develop STA and PNR flows and recommendations addressing aging, self-heating, thermal effects, IR drop, electromigration, and other advanced-node effects.
• Collaborate with technology leads, physical-design engineers, and timing engineers to define and deploy timing-signoff strategies for silicon performance.
• Develop tools and methodologies that improve design performance, predictability, and silicon reliability beyond standard EDA tools.
• Work across STA, constraints, and timing and power optimization.
• Perform extensive data analysis using Python, JMP, or similar tools to improve STA-to-silicon correlation.

Skills

ASIC design

Timing analysis

RC extraction

Device physics

STA methodologies

EDA tools

Clocking techniques

Power analysis

Crosstalk

DVFS

Education

MS in Electrical or Computer Engineering

Tools

PrimeTime

ICC2

RedHawk

Tempus

Job description

Job Requisition ID JR2023669

Job Category Engineering

Time Type Full time

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

What You’ll Be Doing

• Run large-scale SPICE simulations and STA experiments to model the impact of advanced technologies on chip timing.
• Develop STA and PNR flows and recommendations addressing aging, self-heating, thermal effects, IR drop, electro migration, and other advanced-node physical effects.
• Collaborate with technology leads, physical-design engineers, and timing engineers to define and deploy sophisticated timing-signoff strategies for extraordinary silicon performance.
• Develop tools and methodologies that improve design performance, predictability, and silicon reliability beyond the capabilities of standard EDA tools.
• Work across STA, constraints, and timing and power optimization.
• Perform extensive data analysis using Python, JMP, or similar tools to improve STA-to-silicon correlation.

What We Need To See

• MS in Electrical or Computer Engineering, or equivalent experience, with 8 years of experience in ASIC design and timing.
• Solid understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations.
• Proven foundation in the mathematics and physics underlying electrical design.
• Experience with low-power techniques, including multi-Vt design, clock gating, power gating, activity-based power analysis, DVFS, and CDC.
• Understanding of signal and power integrity, crosstalk, electromigration, noise, OCV, timing margins, clock jitter, and IR drop.
• Understanding of standard-cell, memory, and I/O IP modeling and their use in ASIC flows.
• Hands-on experience with advanced FinFET and emerging CMOS technologies at 5 nm, 3 nm, 2 nm, and beyond.
• Familiarity with industry-standard ASIC tools such as PrimeTime, ICC2, RedHawk, and Tempus.
• Strong communication skills and a collaborative working style.

Ways To Stand Out From The Crowd

• Familiarity with 3D IC integration, die stacking and packaging, self-heating, and their impact on timing closure.
• Strong data-analysis and modeling skills employing Python, JMP, or similar platforms.
• Proficiency in Tcl and Python; C++ experience is a plus.

NVIDIA is widely considered one of the technology world's most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're an engineer who thinks in systems, takes pride in designing things that last, and wants to see the silicon your work helps produce — we want to hear from you.

Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until August 24, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.