Senior ASIC Timing Engineer - Equity & GPU/SoC Timing

NVIDIA Corporation; Durham (NC); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an experienced ASIC Timing Engineer in the United States to lead timing analysis and closure for GPUs, CPUs, LPUs, and SoCs at multiple levels. You will collaborate with RTL, DFX, Clocks, and other teams to devise strategies, generate constraints, and drive convergence while implementing ECOs.

The ideal candidate brings hands-on STA experience, ECO expertise, and strong knowledge of timing tools, with deep sub-micron process timing experience.

Qualifications

• BS (or equivalent) in Electrical or Computer Engineering with 5 years’ experience or MS (or equivalent) with 3 years’ experience in Timing and STA.
• Hands-on experience in full-chip/sub-chip STA and timing convergence, timing constraints generation and management.
• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
• Experience in physical design and optimization to improve timing and power.
• Expertise and in-depth knowledge of industry standard STA and timing convergence tools.
• Knowledge of deep sub-micron process nodes and hands-on experience in timing convergence in these nodes.

Responsibilities

• Drive Timing Analysis and Closure: Lead the timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs at block level, cluster level, and full chip level.
• Collaborate with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs.
• Contribute to Cutting-Edge Projects: Play a pivotal role in the success of our innovative projects and advancement of our technology. Leverage your expertise to improve timing convergence flows in collaboration with methodology teams.

Skills

Static Timing Analysis (STA)

Timing closure

ECOs

Physical design

Timing convergence tools

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Job description

NVIDIA is seeking an experienced ASIC Timing Engineer in the United States to lead timing analysis and closure for GPUs, CPUs, LPUs, and SoCs at multiple levels. You will collaborate with RTL, DFX, Clocks, and other teams to devise strategies, generate constraints, and drive convergence while implementing ECOs.

The ideal candidate brings hands-on STA experience, ECO expertise, and strong knowledge of timing tools, with deep sub-micron process timing experience.