Senior ASIC Timing Engineer — Lead Timing Closure

NVIDIA Corporation; Austin (TX); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation is seeking an ASIC Timing Engineer in Austin to lead timing analysis and closure for GPUs, CPUs, LPUs, and SoCs. You will collaborate with RTL, DFX, Clocks, and other teams to implement timing constraints, convergence strategies, and ECOs while advancing timing flows.

A strong background in STA and sub-micron nodes is required. Base salary varies by level (136,000 USD - 218,500 USD for Level 3; 168,000 USD - 264,500 USD for Level 4) plus equity and benefits.

Qualifications

• BS in Electrical or Computer Engineering with 5+ years’ experience or MS with 3+ years’ experience in Timing and STA.
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management.
• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
• Experience in physical design and optimization to improve timing and power.
• Expertise in industry standard STA and timing convergence tools.
• Knowledge of deep sub-micron process nodes and timing convergence for those nodes.

Responsibilities

• Drive Timing Analysis and Closure for NVIDIA GPUs, CPUs, LPUs, and SoCs at block, cluster, and full-chip levels.
• Collaborate with RTL, DFX, Clocks, and other teams to devise timing closure strategies and drive timing/power convergence and ECOs.
• Contribute to cutting-edge projects and improve timing convergence flows in collaboration with methodology teams.

Skills

STA

Timing closure

Power convergence

ECOs

Scripting/Automation

Cross-functional collaboration

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

Synthesis tools

Placement tools

Routing tools

DFT timing tools

Job description

NVIDIA Corporation is seeking an ASIC Timing Engineer in Austin to lead timing analysis and closure for GPUs, CPUs, LPUs, and SoCs. You will collaborate with RTL, DFX, Clocks, and other teams to implement timing constraints, convergence strategies, and ECOs while advancing timing flows.

A strong background in STA and sub-micron nodes is required. Base salary varies by level (136,000 USD - 218,500 USD for Level 3; 168,000 USD - 264,500 USD for Level 4) plus equity and benefits.