ASIC Physical Design CAD Lead — PNR, Flows & Automation

Astera Labs; San Jose (CA); On-site; USD 160,000 - 200,000; Full time

Job summary

Astera Labs in the United States is seeking a Physical Design CAD Engineer to lead ASIC implementation for cloud and AI infrastructure.

You will develop and optimize automated design flows, perform floorplanning, placement, CTS, routing, timing closure, and signoff, and collaborate with cross-functional teams to enable tapeouts.

Strong Python/Tcl scripting and Cadence/Synopsys tool experience are required, with exposure to 7nm or below process nodes preferred.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering; Master's preferred.
• 5+ years of experience in ASIC Physical Design, CAD methodology, or design automation.
• Strong understanding of physical design implementation and RTL-to-GDSII methodologies.

Responsibilities

• Develop and maintain Physical Design CAD flows for advanced process nodes.
• Build automation frameworks using Python and Tcl to support synthesis through signoff.
• Perform hands-on Physical Design and PNR: floorplanning, placement, CTS, routing, timing closure.
• Develop and optimize EDA tool flows for timing analysis, extraction, EM/IR, and physical verification.
• Support block-level implementation from synthesis through GDSII signoff.
• Collaborate with design, verification, and engineering teams to support ASIC tapeout.

Skills

ASIC Physical Design

CAD methodology

Python scripting

Tcl scripting

Timing closure

GDSII signoff

RTL-to-GDSII

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Master's degree preferred

Tools

Cadence tools

Synopsys tools

Innovus

Tempus

Genus

PrimeTime

Fusion Compiler

Job description

Astera Labs in the United States is seeking a Physical Design CAD Engineer to lead ASIC implementation for cloud and AI infrastructure.

You will develop and optimize automated design flows, perform floorplanning, placement, CTS, routing, timing closure, and signoff, and collaborate with cross-functional teams to enable tapeouts.

Strong Python/Tcl scripting and Cadence/Synopsys tool experience are required, with exposure to 7nm or below process nodes preferred.