Senior STA Engineer — AI-Driven Timing & Sign-off

Broadcom, Inc.; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Job summary

Broadcom, Inc. seeks a Principal Physical Design Engineer for STA in the APD team in San Jose, CA. You will own full-chip timing sign-off across PVT corners for next-generation ASICs, leveraging AI-driven automation and MMMC/OCV strategies to meet aggressive performance targets.

You will collaborate with RTL, Physical Design, and DFT teams, develop and maintain SDCs, and drive ECOs and timing closure in a fast-paced, cutting-edge environment.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering required.
• 12+ years of hands-on ASIC STA and timing closure experience.

Responsibilities

• Own final timing closure across PVT corners and maintain SDCs for functional and test modes.
• Deploy AI/ML automation within STA flows to minimize runtime and optimize resources.
• Triaging and isolating root causes to eliminate timing marginalities across complex clock networks and multi-die boundaries.
• Drive timing ECOs and collaborate with RTL, Physical Design, and DFT teams to optimize PPA.

Skills

ASIC STA experience

Timing closure

Sign-off tools (PrimeTime/Tempus)

MMMC/OCV management

Scripting (Tcl, Python, Perl, Shell)

AI/ML automation

Education

Bachelor’s degree in Electrical/Computer Engineering

Tools

PrimeTime

Tempus

OCV

Job description

Broadcom, Inc. seeks a Principal Physical Design Engineer for STA in the APD team in San Jose, CA. You will own full-chip timing sign-off across PVT corners for next-generation ASICs, leveraging AI-driven automation and MMMC/OCV strategies to meet aggressive performance targets.

You will collaborate with RTL, Physical Design, and DFT teams, develop and maintain SDCs, and drive ECOs and timing closure in a fast-paced, cutting-edge environment.