Senior SoC Physical Design Engineer – Onsite San Jose

Inabia Software & Consulting Inc.; San Jose (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Arrow Electronics is seeking a Physical Design Engineer in San Jose, onsite, to execute synthesis, PNR, and STA for ASIC partitions, coordinating with RTL, DFT, and architecture teams.

You will drive EM/IR closure, signoff, and contribute to flows for PD, PDN, LEC, and EMIR, while collaborating with EDA vendors to resolve issues and iterate toward convergence. Candidates should have 7+ years in PD and SoC design, with strong TCL scripting.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 7+ years of hands-on physical design and implementation experience.
• Proficiency with Genus and Innovus and strong understanding of PD flows.
• Experience with timing convergence and physical verification.

Responsibilities

• Execute synthesis, PnR, and STA for ASIC partitions.
• Collaborate with architects, RTL, and DFT to resolve signoff issues.
• Close EM/IR and drive LEC/PDN signoffs with methodology owners.
• Address physical design challenges and iterate flows including EMIR, PDN, and TCL scripts.
• Troubleshoot flows and work with EDA vendors to resolve issues.

Skills

Physical design

Timing convergence

Synthesis/PNR

TCL scripting

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Genus

Innovus

Tempus

Quantus

Job description

Arrow Electronics is seeking a Physical Design Engineer in San Jose, onsite, to execute synthesis, PNR, and STA for ASIC partitions, coordinating with RTL, DFT, and architecture teams.

You will drive EM/IR closure, signoff, and contribute to flows for PD, PDN, LEC, and EMIR, while collaborating with EDA vendors to resolve issues and iterate toward convergence. Candidates should have 7+ years in PD and SoC design, with strong TCL scripting.