Senior STA Engineer: Full-Chip Timing & AI-Driven Flow

Broadcom; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Job summary

Broadcom's ASIC Products Division in San Jose, CA is seeking a Principal Physical Design Engineer specializing in Static Timing Analysis to join the APD team. You will own full‑chip timing sign‑off, applying AI-driven automation and coordinating MMMC/OCV across multi‑die architectures.

You will collaborate with RTL, PD, and DFT teams to optimize PPA, drive ECOs, and ensure timing targets under tight constraints for next‑generation ASICs.

Qualifications

• 12+ years of hands-on ASIC STA and timing closure experience.
• Expert proficiency in sign-off tools PrimeTime/Tempus and MMMC/OCV management.
• Strong scripting skills (Tcl, Python, Perl, Shell) paired with AI plugins and data-mining scripts for runtime reduction and reporting.
• Exceptional problem‑solving and communication abilities.

Responsibilities

• Full‑Chip Timing Sign‑off & Constraints: own final timing closure across PVT corners, authoring and maintaining SDC for functional and test modes.
• AI & Infrastructure Optimization: deploy AI/ML automation within STA flows to minimize execution runtime and maximize resource efficiency.
• Triaging & Marginalities: use automated workflows and data-mining to triage violations and eliminate timing/marginalities across clock networks.
• Methodology, ECOs & Collaboration: drive timing ECOs and partner with RTL, PD, and DFT teams to optimize PPA.

Skills

Scripting (Tcl, Python, Perl, Shell)

AI integration

Data mining

Problem solving

Communication

Education

Bachelor’s degree in Electrical/Computer Engineering

Tools

PrimeTime/Tempus

Job description

Broadcom's ASIC Products Division in San Jose, CA is seeking a Principal Physical Design Engineer specializing in Static Timing Analysis to join the APD team. You will own full‑chip timing sign‑off, applying AI-driven automation and coordinating MMMC/OCV across multi‑die architectures.

You will collaborate with RTL, PD, and DFT teams to optimize PPA, drive ECOs, and ensure timing targets under tight constraints for next‑generation ASICs.