Principal Physical Design Engineer: 3nm/2nm ASICs, Equity

Broadcom; San Jose (CA); Presencial; USD 144.000 - 230.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical benefits

Dental benefits

Vision benefits

401(k) with match

ESPP

Descripción de la vacante

Broadcom's APD division is seeking a Principal Physical Design Engineer to lead block- and top-level implementation for high-performance networking and AI/ML ASICs in San Jose. You will own floorplanning, synthesis, P&R, CTS, timing closure, and sign-off across advanced nodes, collaborating with multi-disciplinary teams to deliver first-pass silicon.

The role requires 12+ years of hands-on PD experience, strong automation skills (TCL/Python), and deep flow mastery.

Formación

• BS or MS in Electrical/Computer Engineering.
• 12+ years of hands‑on physical design experience taping out complex high-frequency ASICs.
• Deep sub-micron tapeout experience on leading nodes (N7/N5/N3) or equivalent.
• Mastery of PD tool flows: P&R, CTS, timing, extraction.
• Automation skills: TCL, Python, Unix shell scripting.
• Excellent technical leadership and cross-functional communication.

Responsabilidades

• Lead block-level and top-level implementation from floorplanning to GDSII using Cadence Innovus.
• Drive floorplanning, placement, CTS, routing, and timing/power optimization on advanced technology nodes.
• Perform MCMM STA, SI optimization, and IR/EM/power integrity for signoff (PrimeTime/Voltus/RedHawk).

Conocimientos

Physical design

ASIC design

P&R

CTS

STA

Scripting

Unix Shell

EDA tools

Educación

B.S./M.S. in Electrical/Computer Engineering

Herramientas

Cadence Innovus

Synopsys PrimeTime

Cadence Tempus

StarRC

QRC

RedHawk

Siemens Calibre

Descripción del empleo

Broadcom's APD division is seeking a Principal Physical Design Engineer to lead block- and top-level implementation for high-performance networking and AI/ML ASICs in San Jose. You will own floorplanning, synthesis, P&R, CTS, timing closure, and sign-off across advanced nodes, collaborating with multi-disciplinary teams to deliver first-pass silicon.

The role requires 12+ years of hands-on PD experience, strong automation skills (TCL/Python), and deep flow mastery.