Senior STA Engineer — ASIC Timing & RTL Expert

eInfochips (An Arrow Company); San Jose (CA); Presencial; USD 140.000 - 220.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

401k, With Matching Contributions

Short-Term/Long-Term Disability Ins.

HSA/HRA Options

Tuition Reimbursement

Descripción de la vacante

eInfochips, an Arrow company, is seeking an experienced timing engineer to develop and verify timing constraints for ASIC designs in a collaborative, cross-functional team. You will work with RTL, verification, synthesis, and DFT groups to resolve timing and implementation issues, ensuring timing closure across modes, including DFT.

Proficiency with STA tools and scripting is required. The role is fully on-site in San Jose, CA, and offers a comprehensive benefits package as part of Arrow's

Formación

• 5+ years of hands-on experience developing and verifying timing constraints.
• Hands-on experience with RTL design.
• Experience debugging PCIe timing constraints and memory timing constraints.
• Experience with CDC/RDC and Conformal verification.

Responsabilidades

• Develop, review, debug, and verify timing constraints for ASIC designs.
• Collaborate with RTL design, verification, synthesis, and DFT teams to resolve timing and implementation issues.
• Analyze timing behavior and support timing closure across functional and test operating modes, including DFT modes.
• Debug timing constraints and reports using industry-standard STA and synthesis tools.

Conocimientos

Timing constraint development

RTL design collaboration

Scripting (Perl Tcl Python)

Debugging timing constraints

DFT timing integration

SDC debugging

PCIe timing constraints

Tool-assisted analysis

Educación

Bachelor's degree in Electrical Eng or related

Master's degree in Electrical Eng or related

PhD in related field

Herramientas

Synopsys PrimeTime STA

Synopsys Fusion Compiler

Synopsys Design Compiler

Synopsys TCM

Tessent (DFT)

Descripción del empleo

eInfochips, an Arrow company, is seeking an experienced timing engineer to develop and verify timing constraints for ASIC designs in a collaborative, cross-functional team. You will work with RTL, verification, synthesis, and DFT groups to resolve timing and implementation issues, ensuring timing closure across modes, including DFT.

Proficiency with STA tools and scripting is required. The role is fully on-site in San Jose, CA, and offers a comprehensive benefits package as part of Arrow's