ASIC STA Engineer: Timing & IP Integration

Apple Inc.; Austin (TX); On-site; USD 100,000 - 130,000; Full time

Job summary

A leading technology company in Austin is seeking an ASIC STA Engineer to oversee timing closure and collaborate with SOC teams. Candidates should possess a Bachelor's degree and have strong fundamentals in digital design. Proficiency in scripting languages such as TCL, Python, and Perl is preferred. This role offers the chance to work on innovative projects that impact millions of customers daily and contribute to hardware technology transformation.

Qualifications

• Bachelor's degree in a relevant field is required.
• Strong fundamentals in digital design are essential.
• Knowledge of ASIC timing concepts is preferred.

Responsibilities

• Own full chip and block level timing closure and constraints.
• Collaborate with SOC teams for design and integration tasks.
• Define and improve front-end design methodologies.

Skills

Digital design fundamentals

Scripting languages (TCL, Python, Perl)

STA tools (Primetime)

Timing constraints writing

Education

Bachelor's Degree

Job description

A leading technology company in Austin is seeking an ASIC STA Engineer to oversee timing closure and collaborate with SOC teams. Candidates should possess a Bachelor's degree and have strong fundamentals in digital design. Proficiency in scripting languages such as TCL, Python, and Perl is preferred. This role offers the chance to work on innovative projects that impact millions of customers daily and contribute to hardware technology transformation.