Senior ASIC Design & SDC Engineer (Full-Chip Timing)

Inabia Software & Consulting Inc.; San Jose (CA); Presencial; USD 140.000 - 190.000; Jornada completa

Descripción de la vacante

Arrow Electronics in San Jose, CA is seeking an experienced ASIC Design/SDC Engineer to own fullchip SDCs and guide timing constraints for seamless physical design closure of next-generation networking chips.

You will collaborate with Front-end and Back-end teams, review block-level SDCs, and mentor RTL designers on SDC development, contributing to efficient methodologies and comprehensive documentation.

Formación

• Minimum 7+ years in ASIC/related field with Bachelor’s or 5+ years with Master’s.
• Experience with block/full-chip SDC development in functional and test modes.
• Experience in Static Timing Analysis with PrimeTime/Tempus.

Responsabilidades

• Oversee fullchip SDCs with design and DFT teams to close timing.
• Mentor RTL designers on SDC development.
• Develop methodologies to promote block-level SDCs to fullchip.
• Create fullchip clocking diagrams and documentation.

Conocimientos

STA expertise

Full-chip SDC

Verilog/SystemVerilog

Python scripting

Clocking analysis

Digital design concepts

Team collaboration

Educación

Bachelor's Degree in Electrical or Computer Engineering

Master's Degree in Electrical or Computer Engineering

Herramientas

PrimeTime

Tempus

Conformal CCD

DC/DCG/FC

Descripción del empleo

Arrow Electronics in San Jose, CA is seeking an experienced ASIC Design/SDC Engineer to own fullchip SDCs and guide timing constraints for seamless physical design closure of next-generation networking chips.

You will collaborate with Front-end and Back-end teams, review block-level SDCs, and mentor RTL designers on SDC development, contributing to efficient methodologies and comprehensive documentation.