Senior ASIC Timing & STA Engineer

AMD; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

AMD is seeking an ASIC Design STA engineer in San Jose, CA, to contribute to the development of large SoCs. Responsibilities include building timing constraints for intricate designs and automating processes for efficiency. The ideal candidate will have extensive experience in SDC, EDA tools like Synopsys Design Compiler and PrimeTime, and strong scripting skills. A Bachelor's or Master's degree in Engineering is required. This role does not offer visa sponsorship but invites diverse applicants.

Qualifications

• Extensive experience in SDC development and debugging.
• Proficiency in both front-end and back-end processes.
• Ability to multitask and adapt to new tools and methodologies.

Responsibilities

• Develop complex timing constraints for RTL and signoff.
• Maintain RTL quality metrics and automate processes.
• Implement pre-route timing checks.
• Collaborate on workflows with CAD.

Skills

SDC expertise

EDA tool proficiency

TCL-based scripting

RTL quality metrics enhancement

Analytical and problem-solving skills

Education

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering

Tools

Synopsys Design Compiler

PrimeTime

Spyglass

Fishtail

Job description

AMD is seeking an ASIC Design STA engineer in San Jose, CA, to contribute to the development of large SoCs. Responsibilities include building timing constraints for intricate designs and automating processes for efficiency. The ideal candidate will have extensive experience in SDC, EDA tools like Synopsys Design Compiler and PrimeTime, and strong scripting skills. A Bachelor's or Master's degree in Engineering is required. This role does not offer visa sponsorship but invites diverse applicants.