Senior SRAM IC Layout Engineer – Advanced CMOS (5nm/3nm)

Rose International; Santa Clara (CA); On-site; USD 152,000 - 165,000; Full time

Job summary

Rose International seeks a Senior SRAM Custom IC Layout Design Engineer in Santa Clara, CA, onsite for a 12-month engagement supporting NVIDIA. The role focuses on complete custom layout of SRAM bitcell arrays, memory periphery, and related macros using advanced CMOS processes.

You will lead floorplanning, DRC/LVS checks with Cadence Virtuoso and Calibre, collaborate with circuit design and PnR teams, ensure layout quality, density, and reliability targets, and mentor junior engineers while

Qualifications

• 10+ years of custom IC layout experience, including 5+ years focused on SRAM, memory compiler, or full-custom memory IP.
• Hands-on experience with advanced CMOS technologies, preferably FinFET or GAA at 5nm, 3nm, or smaller nodes.
• Deep understanding of SRAM and memory layout principles.
• Extensive hands-on experience with Cadence Virtuoso.
• Strong experience with Calibre, ICV, or similar physical-verification tools, including DRC/LVS debugging.
• Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
• Strong knowledge of advanced-node layout considerations including LOD, density/fill, matching, symmetry, shielding, EM/IR, DFM, and layout-dependent effects.

Responsibilities

• Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
• Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
• Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
• Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
• Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
• Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
• Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
• Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
• Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

Skills

CAD

Design

Education

Bachelor’s Degree in Electrical Engineering

Tools

Cadence Virtuoso

Calibre/ICV

DRC/LVS debugging

Job description

Rose International seeks a Senior SRAM Custom IC Layout Design Engineer in Santa Clara, CA, onsite for a 12-month engagement supporting NVIDIA. The role focuses on complete custom layout of SRAM bitcell arrays, memory periphery, and related macros using advanced CMOS processes.

You will lead floorplanning, DRC/LVS checks with Cadence Virtuoso and Calibre, collaborate with circuit design and PnR teams, ensure layout quality, density, and reliability targets, and mentor junior engineers while