Layout Design Engineer

Insight Global; Santa Clara (CA); On-site; USD 138,000 - 153,000; Full time

Job summary

Insight Global is seeking a Sr. SRAM Layout Design Engineer in Santa Clara, CA. The role focuses on complete custom layout for SRAM blocks in advanced CMOS nodes, with heavy emphasis on memory IP and 3 nm+ process technology.

You will verify layouts with DRC/LVS/ERC, collaborate with circuit and PnR teams, and mentor junior engineers to improve layout quality and execution rigor.

Qualifications

• BSEE or equivalent is required.
• 10+ years of custom IC layout experience, incl. 5+ years in SRAM or memory IP layout.
• Experience with advanced CMOS tech nodes (5nm, 3nm or smaller).
• Fab experience preferred, ideally TSMC.
• Memory layout focused (digital SRAM); not analog/mixed-signal.

Responsibilities

• Lead end-to-end SRAM layout for bitcells, memory periphery, test structures, and macros in advanced CMOS tech.
• Develop floorplans for SRAM/memory blocks including array layout, power grids, routing, and macro assembly.
• Perform DRC/LVS/ERC checks and associated physical verification with Calibre/ICV.
• Support EM/IR, power integrity, density, DFM, and tapeout requirements.
• Collaborate with circuit designers to ensure layout targets, matching, shielding, and reliability.

Skills

IC layout

SRAM

Memory IP

CMOS technology

FinFET/GAA

DRC/LVS/EDA

Education

BSEE or equivalent

Tools

Calibre

ICV

Job description

Position: Sr. SRAM Layout Design Engineer

Duration: 12 months + ext

Pay Rate: $100-$111/hr

Work Authorization: W2

Start Date: ASAP

Intv Format: 2 rounds (1 virtual, 1 panel In Person)

Openings: 1

Must Haves:

• Have a BSEE or equivalent experience
• 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
• Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
• Fab experience required. Ideally TSMC.
• Memory Layout design experience required (NOT Analog or mixed signal, must be Digital ideally SRAM)
• 3 nm or more advanced experience required

Plusses:

• Knowledge of layout automation or AI tools is a definite plus.

Day-to-Day:

• Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
• Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
• Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
• Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
• Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
• Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
• Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
• Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
• Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.