Senior SRAM Custom IC Layout Design Engineer

Rose International; Santa Clara (CA); On-site; USD 152,000 - 165,000; Full time

Job summary

Rose International seeks a Senior SRAM Custom IC Layout Design Engineer in Santa Clara, CA, onsite for a 12-month engagement supporting NVIDIA. The role focuses on complete custom layout of SRAM bitcell arrays, memory periphery, and related macros using advanced CMOS processes.

You will lead floorplanning, DRC/LVS checks with Cadence Virtuoso and Calibre, collaborate with circuit design and PnR teams, ensure layout quality, density, and reliability targets, and mentor junior engineers while

Qualifications

• 10+ years of custom IC layout experience, including 5+ years focused on SRAM, memory compiler, or full-custom memory IP.
• Hands-on experience with advanced CMOS technologies, preferably FinFET or GAA at 5nm, 3nm, or smaller nodes.
• Deep understanding of SRAM and memory layout principles.
• Extensive hands-on experience with Cadence Virtuoso.
• Strong experience with Calibre, ICV, or similar physical-verification tools, including DRC/LVS debugging.
• Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
• Strong knowledge of advanced-node layout considerations including LOD, density/fill, matching, symmetry, shielding, EM/IR, DFM, and layout-dependent effects.

Responsibilities

• Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
• Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
• Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
• Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
• Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
• Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
• Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
• Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
• Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

Skills

CAD

Design

Education

Bachelor’s Degree in Electrical Engineering

Tools

Cadence Virtuoso

Calibre/ICV

DRC/LVS debugging

Job description

Date Posted: 09/14/2026

Hiring Organization: Rose International

Position Number: 507433

Industry: IT Company/Software

Job Title: Senior SRAM Custom IC Layout Design Engineer

Job Location: Santa Clara, CA, USA, 95051

Work Model: Onsite

Shift: 8 AM to 5 PM Pacific

Employment Type: Temporary

FT/PT: Full-Time

Estimated Duration (In months): 12

Min Hourly Rate($): 110.00

Max Hourly Rate($): 120.00

Must Have Skills/Attributes: CAD, Design

Experience Desired: Custom IC layout experience, focused on SRAM (10+ yrs); Experience with advanced CMOS technologies, preferably FinFET or GAA at 5nm, 3nm, or smaller nodes (5 yrs); Hands-on experience with Cadence Virtuoso (3 yrs); Experience with Calibre, ICV, or similar physical-verification tools including DRC/LVS debugging (3 yrs)

Required Minimum Education: Bachelor’s Degree

**C2C is not available**

Job Description

*** This role is supporting NVIDIA ***

Education

• Bachelor’s degree in Electrical Engineering (BSEE) or a closely related engineering field, or equivalent relevant experience.

Required Qualifications

• BSEE or equivalent technical experience.
• 10+ years of custom IC layout experience, including 5+ years focused on SRAM, memory compiler, or full-custom memory IP.
• Hands-on experience with advanced CMOS technologies, preferably FinFET or GAA at 5nm, 3nm, or smaller nodes.
• Deep understanding of SRAM and memory layout principles.
• Extensive hands-on experience with Cadence Virtuoso.
• Strong experience with Calibre, ICV, or similar physical-verification tools, including DRC/LVS debugging.
• Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
• Strong knowledge of advanced-node layout considerations including LOD, density/fill, matching, symmetry, shielding, EM/IR, DFM, and layout-dependent effects.
• Ability to work effectively across circuit design, physical design/PnR, integration, CAD, methodology, and foundry teams.
• Strong communication, ownership, technical judgment, and mentoring skills.

Preferred Qualifications

• Experience with layout automation or AI-assisted layout tools.
• Experience developing reusable layout methodologies and automation.
• Experience leading or reviewing complex SRAM/memory layouts through tapeout.

Responsibilities

• Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
• Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
• Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
• Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
• Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
• Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
• Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
• Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
• Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.
• **Only those lawfully authorized to work in the designated country associated with the position will be considered.**
• **Please note that all Position start dates and duration are estimates and may be reduced or lengthened based upon a client’s business needs and requirements.**

Benefits

For information and details on employment benefits offered with this position, please visit here. Should you have any questions/concerns, please contact our HR Department via our secure website.

California Pay Equity

For information and details on pay equity laws in California, please visit the State of California Department of Industrial Relations' website here.

Rose International is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender (expression or identity), national origin, arrest and conviction records, disability, veteran status or any other characteristic protected by law. Positions located in San Francisco and Los Angeles, California will be administered in accordance with their respective Fair Chance Ordinances.

If you need assistance in completing this application, or during any phase of the application, interview, hiring, or employment process, whether due to a disability or otherwise, please contact our HR Department.

Rose International has an official agreement (ID #132522), effective June 30, 2008, with the U.S. Department of Homeland Security, U.S. Citizenship and Immigration Services, Employment Verification Program (E-Verify). (Posting required by OCGA 13/10-91.).