Senior SRAM Layout Engineer - Next-Gen CMOS, Onsite

PeakIT; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

PeakIT seeks a Senior SRAM Layout Design Engineer to own the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies. You will collaborate with circuit, PnR, CAD, and foundry teams to deliver high-quality memory IP on cutting-edge nodes.

This is a senior IC contributor role with mentoring of junior engineers and a focus on layout quality, reliability, and process-technology ramp-up across a multi-year cadence.

Qualifications

• BSEE or equivalent experience.
• 10+ years of hands-on IC layout experience as a senior IC contributor (not a lead/people-management role).
• Hands-on, personal ownership of custom digital SRAM layout; must have directly executed layout themselves.
• Experience with 3nm or more advanced process nodes (TSMC or equivalent).
• Strong grasp of SRAM and memory layout principles.
• Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
• Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar tools.
• Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary management, and top-level verification.
• Knowledge of layout-dependent phenomena (LOD, density/fill, matching, shielding, EM/IR).
• Ability to collaborate with circuit/build/integration teams and mentors.

Responsibilities

• Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
• Develop floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
• Carry out, debug, and complete DRC, LVS, ERC, antenna, and verification checks with Calibre/ICV or similar tools.
• Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and tapeout.
• Collaborate with circuit designers to ensure matching, symmetry, shielding, parasitic targets, and reliability constraints.
• Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro integration issues.
• Implement and advance layout methodology, checklists, reusable practices, and quality standards for memory IP delivery.
• Collaborate with foundry, CAD, and methodology teams on rules, deck behavior, waivers, and advanced-node constraints.
• Review layouts, mentor junior engineers, and raise layout quality and execution rigor across the team.

Skills

Cadence Virtuoso

DRC/LVS debugging

Floorplanning

Macro assembly

Mentoring

Clear communication

Education

BSEE or equivalent

Tools

Calibre

ICV

Cadence Virtuoso

Job description

PeakIT seeks a Senior SRAM Layout Design Engineer to own the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies. You will collaborate with circuit, PnR, CAD, and foundry teams to deliver high-quality memory IP on cutting-edge nodes.

This is a senior IC contributor role with mentoring of junior engineers and a focus on layout quality, reliability, and process-technology ramp-up across a multi-year cadence.