Senior SRAM Layout Engineer — Advanced Memory IP (3nm+)

Tekgence Inc; Santa Clara (CA); On-site; USD 170,000 - 190,000; Part time

Job summary

Tekgence Inc. in Santa Clara, CA seeks a Senior SRAM Layout Design Engineer for a 12‑month contract, onsite at least initially.

You will own the complete custom layout process for SRAM bitcells, memory periphery, test structures, and macros, collaborating with circuit, PnR, CAD, and foundry teams to ensure high-quality memory IP on cutting-edge nodes. You will mentor junior engineers, review layouts, and drive layout quality through verification and best practices.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent is required.
• 10+ years of hands-on IC layout experience, including 5+ years in SRAM/memory IP.
• Direct ownership of SRAM layout in advanced nodes; not suited for mixed-signal.
• Experience with 3nm or beyond; 5nm is a plus; 3nm minimum.
• Proficient with Cadence Virtuoso for custom layout; strong DRC/LVS skills.
• Able to mentor engineers and collaborate across teams.

Responsibilities

• Manage the complete custom layout process for SRAM bitcells and memory macros.
• Develop floorplans, power grid design, routing channels, and macro assembly.
• Perform DRC/LVS/ER C checks using Calibre/ICV and related tools.
• Support EM/IR reviews, density/fill, and tapeout readiness.
• Collaborate with circuit designers to translate schematics into layouts.
• Coordinate with PnR/integration and foundry teams on top‑level verification.

Skills

SRAM layout

Cadence Virtuoso

DRC/LVS debugging

Floorplanning

Macro assembly

Top-level physical verification

EM/IR and DFM considerations

Cross-functional collaboration

Advanced-node process knowledge

Mentoring junior engineers

Education

BSEE or equivalent

Tools

Calibre

ICV

Job description

Tekgence Inc. in Santa Clara, CA seeks a Senior SRAM Layout Design Engineer for a 12‑month contract, onsite at least initially.

You will own the complete custom layout process for SRAM bitcells, memory periphery, test structures, and macros, collaborating with circuit, PnR, CAD, and foundry teams to ensure high-quality memory IP on cutting-edge nodes. You will mentor junior engineers, review layouts, and drive layout quality through verification and best practices.