Senior Formal Verification Engineer - SoC Security & IP

Apple, Inc.; Austin (TX); On-site; USD 150,000 - 278,000; Full time

Benefits offered by this job

Comprehensive medical and dental

Retirement benefits

Employee stock programs

Discounted Apple products

Tuition reimbursement

Relocation assistance

Job summary

Apple Inc. is seeking a Formal Verification Engineer to perform complete formal verification for single or multiple design blocks and IPs including CPU, Cellular and Connectivity IP, and various processing units.

You will work with Security Enclave engineers to define micro-architecture specs and develop verification plans to ensure robustness of the architecture. You will prove properties, detect design bugs, and collaborate with design teams to improve verification efficiency, building

Qualifications

• Bachelor's degree in a relevant field.
• At least 3 years of relevant industry experience in silicon validation software engineering or related field.
• Proficiency in formal verification technologies or methodologies is a plus.

Responsibilities

• Work with Apple Silicon's Security Enclave design engineers to develop a formal micro-architecture specification.
• Develop a comprehensive formal verification test plan including security requirement verification.
• Prove properties of the design, find design bugs, and collaborate with design teams to improve micro-architecture.
• Craft novel solutions for modeling security attacks and proving robustness of complex design micro-architectures.
• Develop and implement reusable and optimized formal models and verification code base.
• Architect correct-by-construction design methodologies for improved verification efficiency.

Skills

Formal verification concepts

Scripting languages

Hardware verification

Bug discovery

Interpersonal skills

Education

Bachelor's degree in a relevant field

Job description

Apple Inc. is seeking a Formal Verification Engineer to perform complete formal verification for single or multiple design blocks and IPs including CPU, Cellular and Connectivity IP, and various processing units.

You will work with Security Enclave engineers to define micro-architecture specs and develop verification plans to ensure robustness of the architecture. You will prove properties, detect design bugs, and collaborate with design teams to improve verification efficiency, building