Senior Design Verification Engineer - SoC & IP

Apple, Inc.; San Diego (CA); On-site; USD 175,000 - 309,000; Full time

Benefits offered by this job

Medical and dental coverage

Employee stock programs

Relocation assistance

Job summary

Apple seeks an outstanding design verification engineer to enable first silicon for IP designs, spanning pre-silicon verification, test-plan development, stimulations, checkers, and RTL tape-out sign-off. You will establish DV methodologies, develop scalable environments, and drive progress with metrics and DV planning.

You will also craft verification plans, execute bring-up, regression enablement, and debug test failures while leveraging LLMs to improve efficiency and quality across the SoC/IP

Qualifications

• BS degree in technical subject with 10+ years of proven experience or equivalent.

Responsibilities

• Study design specification and create test plan
• Develop infrastructure in SystemVerilog/UVM to stress the design
• Develop and fix failures from regressions, close bugs
• Use LLMs to do verification efficiently

Skills

SystemVerilog

UVM

Test bench design

Scripting (Python)

Education

BS degree in engineering or related field

Tools

UVM simulators

Waveform viewers

Automation tools

Power-aware verification (UPF)

Job description

Apple seeks an outstanding design verification engineer to enable first silicon for IP designs, spanning pre-silicon verification, test-plan development, stimulations, checkers, and RTL tape-out sign-off. You will establish DV methodologies, develop scalable environments, and drive progress with metrics and DV planning.

You will also craft verification plans, execute bring-up, regression enablement, and debug test failures while leveraging LLMs to improve efficiency and quality across the SoC/IP