Senior SoC Verification Architect

Quest Global; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Quest Global is seeking a senior design verification engineer in San Jose, CA to verify SOCs with ARM cores, DSPs, DDR3 and interconnects like AHB, AXI and PCIe. You will apply HVL, UVM/SystemVerilog, C/C++, Perl and TCL to create robust verification environments.

The role emphasizes constraint random verification, assertion writing and coverage analysis, with collaboration across divisions and remote locations to deliver high-quality silicon.

Qualifications

• Minimum 8 years of experience required.

Responsibilities

• Design verification of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnects such as AHB, AXI, PCI Express.
• Support HVL verification, constraint random verification, assertion writing and coverage analysis.
• Interface with engineers across divisions and remote locations; collaborate on verification flows.

Skills

UVM/SystemVerilog

C/C++

Perl

TCL scripting

Constraint random

Assertions

Coverage analysis

Formal verification

ARM cores

AMS/Low Power

Tools

EDA tools

FPGA prototyping

Job description

Quest Global is seeking a senior design verification engineer in San Jose, CA to verify SOCs with ARM cores, DSPs, DDR3 and interconnects like AHB, AXI and PCIe. You will apply HVL, UVM/SystemVerilog, C/C++, Perl and TCL to create robust verification environments.

The role emphasizes constraint random verification, assertion writing and coverage analysis, with collaboration across divisions and remote locations to deliver high-quality silicon.