Lead Design Verification Engineer (SOC & Networking)

Veracity Ventures Inc.; Santa Clara (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Veracity Ventures Inc. is seeking a Principal Design Verification Engineer in Santa Clara, CA onsite. You will lead verification for multi-core SoCs, architect the verification environment, and guide a team of engineers on projects.

Responsibilities include building reference models, drivers, and monitors, plus developing tools to streamline design verification. Strong C++, ARM assembly, and Linux knowledge are highly desirable.

Qualifications

• BS in Computer Engineering, Electrical Engineering or Computer Science with 10+ years of verification and firmware/software experience (or MS/PhD with 5+ years).
• Proven track record leading Design Verification implementations and tape-out of complex SOC under tight schedules.
• Deep understanding of SystemVerilog and UVM.
• Experience writing detailed test plans and building directed, random verification environments.
• Experience with Python or Perl and EDA verification tools.
• Experience with Object-Oriented Design and implementation.
• Good Linux OS knowledge; strong C++ and ARM assembly programming skills.
• Understanding of networking protocols is a plus.

Responsibilities

• Write a verification test plan using random techniques and work with designers to ensure completeness.
• Develop tests and tune the environment to achieve coverage goals; debug failures with designers.
• Verify boot code and architect, develop, and maintain tools for scalable SOC design.
• Translate engineering requirements into user-friendly, scalable software tools for parallel compute environments.
• Perform unit and regression testing of software tools.

Skills

SystemVerilog

UVM

Python

Perl

C++

ARM assembly

Object-Oriented Design

Linux

Education

BS in Computer Engineering / Electrical Engineering / Computer Science

MS/PhD with 5+ years experience

Tools

SystemVerilog

UVM

EDA Verification tools

Job description

Veracity Ventures Inc. is seeking a Principal Design Verification Engineer in Santa Clara, CA onsite. You will lead verification for multi-core SoCs, architect the verification environment, and guide a team of engineers on projects.

Responsibilities include building reference models, drivers, and monitors, plus developing tools to streamline design verification. Strong C++, ARM assembly, and Linux knowledge are highly desirable.