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Quest Global is seeking a senior design verification engineer in San Jose, CA to verify SOCs with ARM cores, DSPs, DDR3 and interconnects like AHB, AXI and PCIe. You will apply HVL, UVM/SystemVerilog, C/C++, Perl and TCL to create robust verification environments.
The role emphasizes constraint random verification, assertion writing and coverage analysis, with collaboration across divisions and remote locations to deliver high-quality silicon.
\"\"MINIMUM 08 YEARS OF EXPERIENCE REQUIRED\"\"