Senior SoC RTL Engineer - PPA & Subsystem Expert

QUADRIC PTY LTD; Burlingame (CA); On-site; USD 170,000 - 230,000; Full time

Benefits offered by this job

Medical/Dental/Vision Insurance

Company-paid Life Insurance

Flex PTO

401(k) Retirement Plan

Catered lunch daily

Downtown Burlingame office

Equity with the business

Parental Leave

Caltrain/parking reimbursement

Job summary

Quadric, based in Burlingame, CA, is redefining edge AI with its GPNPU and invites a Staff SoC RTL Engineer to shape the architecture, own subsystem development, integrate third-party IP, and drive PPA optimization to bring the next-generation platform to life.

In this role you will contribute across all design stages, ensure timing closure, and package releases for customer evaluation. 5+ years in SoC/ASIC front-end is required.

Qualifications

• BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 5+ years of hands-on SoC/ASIC front-end design and integration experience.
• Proficiency in SystemVerilog or Verilog.
• Strong background in computer architecture, low-power digital design techniques, and deep technical knowledge in at least one subsystem (Memory, I/O, or Compute).
• Proven experience with SoC subsystems (including 3rd-party IP) and working knowledge of VCS & Verilog/C Co-Simulation.

Responsibilities

• Own SoC-level subsystem development and seamless integration with third-party IP (such as NoC, PCIe/UCIe interfaces, DDR, Security, etc.).
• Contribute directly to the definition of the SoC architecture by deeply understanding its application requirements.
• Package designs for customer releases and rapidly iterate based on customer feedback.
• Own Power, Performance, and Area (PPA) optimization strategies at the SoC level.
• Apply low-power digital design techniques to optimize hardware efficiency.
• Contribute to timing closure across the full product lifecycle, spanning front-end, back-end, and final tapeout stages.
• Balance single-stream latency against scaled throughput performance.

Skills

SystemVerilog

Verilog

SoC Architecture

IP Integration

VCS

Low-power Design

Front-end Design

Education

BS/MS/PhD in Electrical or Computer Engineering

Tools

VCS

Verilog Co-Simulation

NoC/PCIe/IP Integration

FPGA Tools

Job description

Quadric, based in Burlingame, CA, is redefining edge AI with its GPNPU and invites a Staff SoC RTL Engineer to shape the architecture, own subsystem development, integrate third-party IP, and drive PPA optimization to bring the next-generation platform to life.

In this role you will contribute across all design stages, ensure timing closure, and package releases for customer evaluation. 5+ years in SoC/ASIC front-end is required.