Edge SoC Design Intern - Verilog, PPA & SoC Subsystems

quadric, Inc; Burlingame (CA); On-site; USD 69,000 - 79,000; Full time

Benefits offered by this job

Catered lunch

Downtown Burlingame

Disruptive culture

Job summary

Quadric is building edge AI with a GPNPU; we’re seeking a motivated intern to join the Burlingame team, contributing to SoC subsystem development and integrating third‑party IP. You’ll help optimize PPA and work with architects on front-end design, gaining hands-on experience in a real FPGA/ASIC environment.

You will collaborate with engineers on subsystem integration, verify design intent, and document technical decisions while developing proficiency in SystemVerilog/Verilog and Python

Qualifications

• Pursuing a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Familiarity with SoC/ASIC front-end design concepts.
• Proficient in SystemVerilog or Verilog.
• Prepared to collaborate with architects and designers on subsystem development and integration tasks.
• Demonstrated capability in problem-solving, debugging, and clear technical communication.

Responsibilities

• Support SoC Subsystem Development and integration of subsystems and third-party IP.
• Assist in analyzing and optimizing Power, Performance, and Area (PPA) at the SoC level.
• Collaborate closely with SoC architects/designers and communicate findings clearly.

Skills

SystemVerilog

SoC frontend design

Problem-solving

Technical communication

Python scripting

Education

Bachelor's / Master’s / PhD in Electrical Engineering or Computer Engineering

Job description

Quadric is building edge AI with a GPNPU; we’re seeking a motivated intern to join the Burlingame team, contributing to SoC subsystem development and integrating third‑party IP. You’ll help optimize PPA and work with architects on front-end design, gaining hands-on experience in a real FPGA/ASIC environment.

You will collaborate with engineers on subsystem integration, verify design intent, and document technical decisions while developing proficiency in SystemVerilog/Verilog and Python